This invention relates to apparatus and method for holding and planarizing thin workpieces, and more specifically to vacuum apparatus for holding semiconductor wafers during pattern exposure in photolithography.
The invention also relates to a method for fabricating devices on a semiconductive wafer by utilizing such an apparatus.
Recent advances in large scale integration (LSI) of semiconductor circuits have been made possible largely by higher resolution photolithography which permits finer features to be patterned onto a semiconductor surface. Consequently circuit components can be made smaller, thus making it possible to place an increasing number of components onto a single semiconductor chip. The results are circuits of greater complexity, higher speed, lower power dissipation and lower cost.
As a practical matter, the feature size limitations in photolithography are not usually imposed by the resolution capabilities of the optical components nor by that of the photoresist, but rather by the flatness or planarity of the semiconductor surface being patterned. The consequence of nonplanarity is distortion of the pattern being exposed and an error in the focal position. Surface planarity is particularly important when projection printing is used where, to achieve the maximum resolution capability of the projection optics, the semiconductor surface being exposed must be made essentially coincident with the focal plane of the projection optics. Deviations of the surface from the focal plane must not exceed the depth of focus of the optical system. For example, if the total depth of focus were 10 microns, then to achieve maximum resolution, the semiconductor surface including a photoresist film approximately one micron thick must be maintained planar to within 10 microns during pattern exposure. A high degree of surface planarity is also required to achieve freedom from pattern distortion in contact printing and maximum pattern resolution in proximity printing although the requirement is not as critical as for projection printing.
Nonplanarity in semiconductor wafers may be separated into two sources. The first is that of nonlinear thickness variations in the wafer. Normally during pattern exposure, one surface of the wafer (back surface) is forced to substantially conform to a planar surface by some wafer holding apparatus. Thus, the other surface of the wafer (front surface) would be planar if the wafer had no nonlinear thickness variation. Notice that if the wafer had a linear thickness variation (e.g. a wedge shape), its front surface would still be planar although it would not be parallel with the back surface. This can be tolerated by most projection and proximity printing systems which have means for tilting the wafer surface to make it parallel to the optical plane of the printing system. But, if the wafer had a nonlinear thickness variation, its front surface would be nonplanar. However, nonlinear thickness variations can be reduced to an acceptable degree by careful wafer fabrication.
The second source of nonplanarity in semiconductor wafers is that of warpage. Owing to the thinness of semiconductor wafers used for intergrated circuit processing, some warpage is always present. A typical three inch diameter silicon wafer which has a thickness of fifteen to twenty thousandths of an inch may exhibit a warpage of as much as two thousandths of an inch or approximately fifty microns. Warpage is first introduced when the wafer is sawed from the boule. Because the thin wafer is rather springy, the warpage is not removed by the subsequent lapping and polishing steps in the wafer fabrication process. Furthermore, the furnace sequences and the growth and deposition of various films on the wafer surface during the device fabrication process may all aggravate the warpage.
The usual method for removing wafer warpage during pattern exposure is to hold the wafer on a vacuum holding apparatus with a highly planar holding face. Thus, if the wafer warpage were not too severe, (less than fifty microns), and if the wafer had minimal nonlinear thickness variation, the vacuum holding apparatus would in principle cause the front surface to have a high order of planarity.
However, a problem arises when dirt particles become interposed between the wafer and the holding face to prevent intimate contact. Since the size of dirt particles may be ten microns in diameter or greater, their effect is to cause the wafer front surface to deviate sufficiently from planarity to produce pattern distortion during photolithographic exposure. The problem of dirt particles is especially difficult to solve in a manufacturing environment where the necessity to maintain a high throughput of wafers through each photolithographic step renders any cleaning procedure to remove dirt particles from the wafer and the wafer holder impractical. Moreover, removal of particulates from the air as in an "ultra-clean room" environment does not completely solve the problem as most of the dirt particles come from the wafers themselves in the form of chips from the wafer edges and flakes from films grown or deposited on the wafer surface. A broken wafer causes the most severe contamination of particles.
Vacuum fixtures for holding thin workpieces are disclosed in U.S. Pat. Nos. 3,627,338, and 3,747,282. Both patents disclose vacuum chucks where the workpiece holding face comprises a planar surface with annular and radial grooves for distributing vacuum to the back surface of the workpiece. Furthermore, these known fixtures were apparently devised for applications in machining and polishing of thin workpieces where the requirements for workpiece planarity is not as critical as for photolithography. Therefore, none of the above-mentioned disclosures offers any solutions to the problems arising from the wafer planarity requirements imposed by photolithography and the detrimental effects of dirt particles on achieving that planarity.
From the foregoing, a need clearly exists for a vacuum wafer holding apparatus and wafer planarization method which is substantially immune to dirt particles which are always present in a semiconductor device manufacturing environment.